1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of minimizing a distortion of a common voltage and a method of driving the same.
2. Discussion of the Related Art
Liquid crystal display devices (LCDs) display an image by controlling a light transmittance of liquid crystal cells in accordance with video signals. An active matrix type LCD having thin film transistors (TFTs) at each liquid crystal cell is suited for displaying moving images.
FIG. 1 is a plan view of a related art LCD. As illustrated in FIG. 1, the related art LCD includes a liquid crystal panel 2, a plurality of data tape carrier packages (TCPs) 4 connected between the liquid crystal panel 2 and a data printed circuit board (PCB) 8, a plurality of data driver integrated circuits (ICs) 6 mounted on each of data TCPs, a timing controller 16 built in the data PCB 8, a plurality of gate TCPs 10 connected to another side of the liquid crystal panel 2, and a plurality of gate driver ICs 12 integrated in each of the gate TCPs 10.
A pixel region of the liquid crystal panel 2 is defined at each intersection of a plurality of gate lines GL0 to GLn and a plurality of data lines DL1 to DLm. The TFTs and pixel electrodes are formed on the pixel regions. A display region 17 is defined by the plurality of pixel regions, and a non-display region 19 is defined by regions outside the display region 17. A data pad (not shown) connected to the data TCP 4 and a data link (not shown) for connecting the data pad with the corresponding data line are disposed in an outer region of the display region 17, namely, the non-display region 19. Additionally, a gate pad (not shown) connected to the gate TCP 10 and a gate link (not shown) for connecting the gate pad with the corresponding gate line are disposed in the non-display region 19. Common voltage (Vcom) supply lines 13 are disposed in parallel to the respective gate lines GL0 to GLn on the display region 17.
The liquid crystal panel 2 includes a lower substrate 1 and an upper substrate 3 each having a transparent insulating substrate, and liquid crystal (not shown) injected between the lower substrate 1 and the upper substrate 3. A LOG-type signal line group 14 is formed on the lower substrate 1 to connect in series a gate driver IC 12 mounted on the gate TCP 10 to a data TCP 4 in the non-display region 19. More specifically, the LOG-type signal line group 14 is disposed between a first data TCP 4 and a first gate TCP 10 to supply gate control signals and gate voltages supplied from an external source to the first gate TCP 10 through the data PCB 8 and the first data TCP 4.
Each of the gate driver ICs 12 supplies a gate high voltage VGH to the corresponding gate lines GL1 to GLn sequentially in response to a gate control signal supplied from the timing controller 16. Each of the data driver ICs 6 supplies a data voltage of corresponding data lines DL1 to DLm at each horizontal period H1 to Hm in response to a data control signal from the timing controller 16. The timing controller 16 generates the gate control signal controlling the gate driver ICs 12 and the data control signal controlling the data driver ICs 6.
A common voltage generator 18 generates a common voltage Vcom to drive the liquid crystal panel 2 using a power voltage Vdd generated from a DC/DC converter (not shown). The common voltage Vcom is supplied to the common voltage supply lines 13 on the liquid crystal panel 2. The common voltage supply lines 13 and gate lines GL0 to GLn are formed on the same layer, and then a gate insulating layer is formed over the lines. The data lines DL1 to DLm are then formed on the gate insulating layer. As a result, a capacitance is formed between the common voltage supply lines 13 and the data lines DL1 to DLm due to the presence of the gate insulating layer between the common voltage supply lines 13 and the data lines DL1 to DLm.
Accordingly, when a data signal value between the data lines DL1 to DLm changes drastically, a ripple is generated in the common voltage Vcom that is supplied to the common voltage supply lines 13 by the capacitance. A crosstalk phenomenon is generated on the liquid crystal panel 2 due to the common voltage Vcom distorted by the ripple. Therefore, a common voltage Vcom compensator 20 is configured to prevent this crosstalk phenomenon.
The common voltage Vcom compensator 20 compensates the distorted common voltage and supplies a compensated common voltage to the liquid crystal panel 2 in the following manner. When the common voltage Vcom is supplied to the liquid crystal panel 2 during one frame, the common voltage Vcom becomes distorted by the capacitance between the common voltage supply line 13 and the data lines DL1 to DLm, thereby causing a ripple in the common voltage Vcom. During the next frame, the common voltage Vcom compensator 20 receives the distorted common voltage in a feedback loop on the liquid crystal panel 2, compensates the distorted common voltage, and supplies the compensated common voltage to the liquid crystal panel 2.
However, the amount of distortion of the common voltage Vcom generated is different in the top, middle, and bottom sections of the liquid crystal panel 2 due to load characteristics of the liquid crystal panel 2. That is, the degree of distortion of the common voltage Vcom in the top, middle, and bottom sections of the liquid crystal panel 2 changes as the size of the liquid crystal panel 2 or the line resistance of the common voltage supply lines 13 increases. Therefore, the distortion of the common voltage Vcom cannot be reduced in all sections of the liquid crystal panel 2 (i.e., the top, middle, and bottom sections of liquid crystal panel 2). Accordingly, although the related art LCD partially compensates for the distortion of the common voltage Vcom supplied to the liquid crystal panel 2, the distortion of the common voltage Vcom cannot be compensated for the entire region of the liquid crystal panel 2. Consequently, the image quality of the related art LCD suffers.